Introduction To SystemVerilog

Verilog version 1995 has been in market for a very long time. Later in 2001 came Verilog 2001. Verilog however, could not satisfy the demands of the verification engineers, and other languages like “e” and VERA have surfaced. SystemVerilog aim was to combine the Verification capabilties of the verification languages with the syntax of Verilog and to provide a single platform for both design and verification.

It was developed originally by Accellera to dramatically improve productivity in the design of large gate-count, IP-based, bus-intensive chips. SystemVerilog is targeted primarily at the chip implementation and verification flow, with powerful links to the system-level design flow. SystemVerilog has been adopted by 100′s of semiconductor design companies and supported by more than 75 EDA, IP and training solutions worldwide.